The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Oct. 04, 2023
Applicant:
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;
Inventors:
Assignee:
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); G11C 5/06 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); G11C 5/063 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10B 12/50 (2023.02);
Abstract
A memory structure includes a substrate, a first device layer disposed on the substrate, a plurality of memory regions in the first device layer, a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions, a second device layer disposed between the substrate and the first device layer, and first peripheral regions and second peripheral regions in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions.