The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Dec. 09, 2020
Hangzhou Weiming Xinke Technology Co., Ltd, Zhejiang, CN;
Advanced Institute of Information Technology (Aiit), Peking University, Zhejiang, CN;
Le Ye, Zhejiang, CN;
Zhixuan Wang, Zhejiang, CN;
Qianqian Huang, Zhejiang, CN;
Yangyuan Wang, Zhejiang, CN;
Ru Huang, Zhejiang, CN;
HANGZHOU WEIMING XINKE TECHNOLOGY CO., LTD, Zhejiang, CN;
ADVANCED INSTITUTE OF INFORMATION TECHNOLOGY (AIIT), PEKING UNIVERSITY, Zhejiang, CN;
Abstract
Disclosed in the present application are a logic circuit design method and apparatus, and a storage medium. The method comprises: designing and generating an initial MOSFET-TFET hybrid logic circuit, the MOSFET-TFET hybrid logic circuit comprising several logic gates; in the series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with a MOSFET; the first type of TFET being directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates. The logic circuit design method of the present application overcomes the defect of excessive current attenuation caused by the TFET in the series branch by replacing the first type of TFET in the series branch of the initial logic circuit with a MOSFET. The first type of TFET is a TFET that is directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates.