The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Dec. 22, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andy Chih-Hung Wei, Yamhill, OR (US);

Guillaume Bouche, Hillsboro, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/6211 (2025.01); H10D 30/797 (2025.01); H10D 84/834 (2025.01);
Abstract

Gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires include silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure.


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