The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Sep. 12, 2022
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Jih-Wen Chou, Hsinchu, TW;

Hsin-Hong Chen, Hsinchu, TW;

Yu-Jen Huang, Hsinchu, TW;

Robin Christine Hwang, Taipei, TW;

Po-Hsien Yeh, Hsinchu County, TW;

Chih-Hung Lu, Taichung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/285 (2006.01); H01L 23/31 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/27 (2025.01); H10D 64/64 (2025.01);
U.S. Cl.
CPC ...
H10D 30/675 (2025.01); H01L 21/28581 (2013.01); H01L 21/28587 (2013.01); H01L 23/3192 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 30/6738 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 62/8503 (2025.01); H10D 64/411 (2025.01); H10D 64/64 (2025.01);
Abstract

A high electron mobility transistor device including a channel layer, a first barrier layer, a gate structure, and a spacer is provided. The first barrier layer is disposed on the channel layer. The gate structure is disposed on the first barrier layer. The gate structure includes a first P-type gallium nitride layer, a second barrier layer, and a second P-type gallium nitride layer. The first P-type gallium nitride layer is disposed on the first barrier layer. The second barrier layer is disposed on the first P-type gallium nitride layer. The second P-type gallium nitride layer is disposed on the second barrier layer. A width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer. The spacer is disposed on a sidewall of the second P-type gallium nitride layer.


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