The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Oct. 09, 2024
Applicant:

Hefei Reliance Memory Limited, Hefei, CN;

Inventors:

Chao-Yang Chen, Hefei, CN;

Wen-Hsiung Chang, Hefei, CN;

Zezhi Chen, Hefei, CN;

Zhichao Lu, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/22 (2023.02); H10N 70/021 (2023.02); H10N 70/20 (2023.02); H10N 70/841 (2023.02);
Abstract

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.


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