The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

May. 18, 2023
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Hang-Ting Lue, Hsinchu, TW;

Teng-Hao Yeh, Hsinchu, TW;

Wei-Chen Chen, Taoyuan, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3495 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/30 (2013.01);
Abstract

An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be 'snaked' through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.


Find Patent Forward Citations

Loading…