The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Nov. 16, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Ting Chung, Hsinchu, TW;

Chien-Hong Chen, Hsinchu County, TW;

Mahaveer Sathaiya Dhanyakumar, Hsinchu, TW;

Hou-Yu Chen, Hsinchu County, TW;

Jin Cai, Hsinchu, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 64/01 (2025.01); H10K 10/46 (2023.01); H10K 10/84 (2023.01); H10K 85/20 (2023.01);
U.S. Cl.
CPC ...
H10D 64/259 (2025.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10D 64/01 (2025.01); H10K 10/484 (2023.02); H10K 10/84 (2023.02); H10K 85/221 (2023.02);
Abstract

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.


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