The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Mar. 31, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Zhiqiang Wu, Zhubei, TW;

Kuo-An Liu, Hsinchu, TW;

Kai Tak Lam, Hsinchu, TW;

Meng-Yu Lin, New Taipei, TW;

Chun-Fu Cheng, Zhubei, TW;

Chieh-Chun Chiang, Taipei, TW;

Chun-Hsiang Fan, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0243 (2025.01); H10D 30/6211 (2025.01); H10D 64/021 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 30/6219 (2025.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a fin, and a semiconductor layer. The fin is over the substrate, the semiconductor layer is over the fin, the substrate and the fin are made of different materials, and the fin and the semiconductor layer are made of different materials. The method includes forming a dielectric layer over the semiconductor layer and the fin. The method includes forming a semiconductor structure over a sidewall of the dielectric layer. The method includes removing a first top portion of the dielectric layer over a top surface of the semiconductor layer. The method includes forming a gate over the semiconductor layer, the dielectric layer, and the semiconductor structure.


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