Memory device and fabrication method thereof

Abstract

A memory device fabrication method includes providing a semiconductor structure having a core area and a contact area arranged next to each other along a first direction. The semiconductor structure includes dielectric layer pairs that include first and second dielectric layers stacked in an alternating manner in a second direction approximately perpendicular to the first direction. The method further includes performing etching to form channel holes penetrating the dielectric layer pairs. The channel holes include first channel holes in the contact area and second channel holes in the core area. The first channel holes surround a contact region. The method also includes substituting portions of the second dielectric layers that surround the plurality of first channel holes with a protection material to form a protection wall that surrounds the contact region.