Technologies for fabricating a vertical dram structure

Abstract

Technologies for fabricating a vertical dynamic random access memory (DRAM) structure include forming a DRAM cell hole through a word line layer and an associated substrate such that a first section of the DRAM cell hole extends through the word line layer and a second section of the DRAM cell hole extends through the substrate in vertical alignment with the first section. A pillar capacitor structure is initially formed using the second section of the DRAM cell hole, followed by the formation of a transistor using the first section of the DRAM cell hole as a channel for the transistor. Due to the use of a common DRAM cell hole, the pillar capacitor structure and the channel are in vertical alignment. The substrate is subsequently flipped and removed from the pillar capacitor structure, which is further processed to form a pillar capacitor. In some embodiments, the channel may be formed from a deposition of indium gallium zinc oxide (IGZO).