The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2025
Filed:
Aug. 07, 2023
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Wen-Kai Lin, Hsinchu, TW;
Che-Hao Chang, Hsinchu, TW;
Chi On Chui, Hsinchu, TW;
Yung-Cheng Lu, Hsinchu, TW;
Szu-Ying Chen, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/02 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 64/018 (2025.01); H01L 21/0228 (2013.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01);
Abstract
A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl)CH), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.