The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jul. 01, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Mrunal A. Khaderbad, Hsinchu, TW;

Keng-Chu Lin, Ping-Tung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/768 (2006.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/024 (2025.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 64/01 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

The structure of a semiconductor device with source/drain contact structures and via structures and a method of fabricating the semiconductor device are disclosed. A method for fabricating a semiconductor device includes forming a source/drain (S/D) region on a substrate, forming a S/D contact structure on the S/D region, and forming a via structure on the S/D contact structure. The forming of the via structure includes forming a via opening on the S/D contact structure, forming a non-metal passivation layer on sidewalls of the via opening, and depositing a via plug within the via opening in a bottom-up deposition process.


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