The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Sep. 22, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Semyeong Jang, Hefei, CN;

Joonsuk Moon, Hefei, CN;

Deyuan Xiao, Hefei, CN;

Minki Hong, Hefei, CN;

Kyongtaek Lee, Hefei, CN;

Jo-Lan Chin, Hefei, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10B 12/00 (2023.02); H10B 12/01 (2023.02); H10B 12/0335 (2023.02); H10B 12/0383 (2023.02); H10B 12/0387 (2023.02); H10B 12/053 (2023.02); H10B 12/315 (2023.02); H10B 12/395 (2023.02); H10B 12/488 (2023.02); H10D 30/025 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 62/122 (2025.01); H10D 64/252 (2025.01); H10D 64/512 (2025.01); H10D 64/513 (2025.01); H10D 64/517 (2025.01); H10D 64/518 (2025.01); H10D 64/519 (2025.01); H10B 12/05 (2023.02); H10D 30/6757 (2025.01); H10D 84/0172 (2025.01); H10D 84/0179 (2025.01);
Abstract

A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.


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