The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Sep. 06, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Biswanath Senapati, Mechanicville, NY (US);

Seiji Munetoh, Tokyo, JP;

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Geoffrey Burr, Cupertino, CA (US);

Kohji Hosokawa, Ohtsu, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02);
Abstract

An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.


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