The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jul. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Li-Zhen Yu, New Taipei, TW;

Huan-Chieh Su, Tianzhong Township, TW;

Lin-Yu Huang, Hsinchu, TW;

Cheng-Chi Chuang, New Taipei, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/76283 (2013.01); H01L 21/76877 (2013.01); H01L 23/5286 (2013.01); H10D 30/6219 (2025.01); H10D 64/021 (2025.01); H01L 21/31116 (2013.01); H01L 21/31122 (2013.01); H01L 23/5226 (2013.01); H10D 30/026 (2025.01); H10D 30/031 (2025.01); H10D 64/018 (2025.01);
Abstract

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.


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