The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jul. 26, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei-Xiang You, Kaohsiung, TW;

Szuya Liao, Hsinchu, TW;

Cheng-Yin Wang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G11C 11/419 (2006.01); H03K 19/20 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/419 (2013.01); H03K 19/20 (2013.01); H10B 10/125 (2023.02);
Abstract

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.


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