The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jun. 20, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Chuanjiang Chen, Hefei, CN;

Kang Zhao, Hefei, CN;

Li Bai, Hefei, CN;

Li Tang, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 119/06 (2020.01); G06F 119/18 (2020.01); H01L 23/52 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06F 2119/18 (2020.01); H01L 23/5283 (2013.01);
Abstract

The present disclosure relates to a layout repairing method and apparatus, a computer device, and a storage medium. The method includes: obtaining an initial layout of a semiconductor integrated circuit, wherein a metal connection line is formed on the initial layout; forming a power fill grid on the initial layout, wherein the power fill grid includes a slotted hole that overlaps orthographic projection of the metal connection line on the power fill grid, and the slotted hole includes a first section overlapping the metal connection line and at least one second section staggered with the metal connection line; and increasing area of the second section if the area of the second section is less than a lower threshold, to form a repaired layout.


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