The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Feb. 12, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chen Hsiung Yang, Hsinchu County, TW;

Chun-Wen Cheng, Hsinchu County, TW;

Chia-Hua Chu, Hsinchu County, TW;

En-Chan Chen, Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81B 3/00 (2006.01); B81B 7/00 (2006.01); B81B 7/02 (2006.01); B81C 1/00 (2006.01); H04R 19/00 (2006.01); H04R 19/04 (2006.01); H04R 31/00 (2006.01);
U.S. Cl.
CPC ...
B81B 3/0051 (2013.01); B81B 3/0064 (2013.01); B81B 3/007 (2013.01); B81B 7/0009 (2013.01); B81B 7/0061 (2013.01); B81B 7/02 (2013.01); B81C 1/00158 (2013.01); H04R 19/005 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0307 (2013.01); B81B 2203/0361 (2013.01); H04R 19/04 (2013.01); H04R 31/00 (2013.01); H04R 2201/003 (2013.01);
Abstract

A MEMS device includes a first multi-layer structure, a second multi-layer structure over the first multi-layer structure, a first semiconductor layer between the first and second multilayer structures, a first air gap separating the first multi-layer structure and the first semiconductor layer, a second air gap separating the first semiconductor layer and the second multi-layer structure, a plurality of semiconductor pillars, and a plurality of second semiconductor pillars. The first semiconductor pillars are exposed to the first air gap, and coupled to the first semiconductor layer and the first multi-layer structure. The second semiconductor pillars are exposed to the second air gap, and coupled to the first semiconductor layer and the second multi-layer structure.


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