The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Sep. 22, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jian-Sing Li, Hsinchu, TW;

Guo-Huei Wu, Tainan, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Chih-Liang Chen, Hsinchu, TW;

Li-Chun Tien, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); G06F 30/392 (2020.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/392 (2020.01); H01L 21/02603 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01);
Abstract

An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.


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