The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Oct. 04, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Brent A. Anderson, Jericho, VT (US);

Kisik Choi, Watervliet, NY (US);

Su Chen Fan, Cohoes, NY (US);

Shogo Mochizuki, Mechanicville, NY (US);

Son Nguyen, Schenectady, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6729 (2025.01); H01L 23/5286 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01);
Abstract

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.


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