The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Aug. 01, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Jhon-Jhy Liaw, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); H10B 10/00 (2023.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); G11C 11/412 (2013.01); H10B 10/125 (2023.02); H10D 89/10 (2025.01);
Abstract

An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.


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