The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Mar. 13, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hai-Dang Trinh, Hsinchu, TW;

Chii-Ming Wu, Taipei, TW;

Hsing-Lien Lin, Hsin-Chu, TW;

Fa-Shen Jiang, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H01L 23/528 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10N 70/841 (2023.02); H01L 23/528 (2013.01); H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/8833 (2023.02); H10N 70/8836 (2023.02);
Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode structure disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. The bottom electrode structure has an upper surface including a noble metal. A diffusion barrier layer is over the bottom electrode structure, a data storage structure is over the diffusion barrier layer, and a top electrode structure is over the data storage structure. The diffusion barrier layer is configured to mitigate a diffusion of noble metal atoms from the bottom electrode structure to the data storage structure.


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