The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Jun. 06, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ko-Cheng Liu, Hsinchu, TW;

Chang-Miao Liu, Hsinchu, TW;

Ming-Lung Cheng, Kaohsiung County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01);
Abstract

An exemplary device includes a stack of channel layers over a substrate extension, a gate, and an insulation layer. The stack of channel layers extends between a first epitaxial source/drain and a second epitaxial source/drain. The gate surrounds each channel layer of the stack of the channel layers. The insulation layer is over the substrate extension, the gate is between a bottommost channel layer of the stack of channel layers and the insulation layer, and the insulation layer is between the gate and the substrate extension. The insulation layer extends between the first epitaxial source/drain and the second epitaxial source/drain, each of which may include an undoped epitaxial layer. A top surface of the undoped epitaxial layer is below a bottom surface of the bottommost channel layer and/or above a top surface of the insulation layer. The insulation layer may wrap the substrate extension and/or have an air gap therein.


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