The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2025
Filed:
Apr. 28, 2023
Kepler Computing Inc., San Francisco, CA (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Pramod Kolar, Cary, NC (US);
Mustansir Yunus Mukadam, Seattle, WA (US);
Darshak Doshi, Sunnyvale, CA (US);
Biswajeet Guha, Hillsboro, OR (US);
Tanay Gosavi, Portland, OR (US);
Amrita Mathuriya, Portland, OR (US);
Debo Olaosebikan, San Francisco, CA (US);
Sasikanth Manipatruni, Portland, OR (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
Described herein is a read and write scheme to improve memory reliability. In at least one embodiment, one or more circuitries are provided to perform logic 0 write operation in a first phase and logic 1 write operation in a second phase for a plurality of bit-cells controlled by a word-line. In at least one embodiment, an individual bit-cell comprises a transistor having a gate terminal coupled to the word-line; and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein a source or drain terminal of the transistor is coupled to a bit-line.