The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Aug. 31, 2022
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Vivek Chickermane, Slaterville Springs, NY (US);

Christos Papameletis, Apex, NC (US);

Brian Foutz, Charlottesville, VA (US);

Krishna V. Chakravadhanula, Vestal, NY (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 11/10 (2006.01); G06F 11/14 (2006.01); G06F 11/16 (2006.01); G06F 11/27 (2006.01); G06F 11/273 (2006.01); H01L 25/00 (2006.01); G06F 115/08 (2020.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 11/10 (2013.01); G06F 11/14 (2013.01); G06F 11/16 (2013.01); G06F 11/27 (2013.01); G06F 11/273 (2013.01); G06F 2115/08 (2020.01); H01L 22/00 (2013.01); H01L 25/00 (2013.01);
Abstract

An integrated circuit (IC) chip includes an intellectual property (IP) core that executes logical operations to perform a function. The IC chip also includes a scan chain array for testing the IP core, and a pseudo random pattern generator (PRPG) that provides a pseudo random pattern based on a seed. The IC chip includes a spreader network that applies a first pseudo random code to a first edge of a die of the IC chip and a second pseudo random code to a second edge of the die of the IC chip in response to the pseudo random pattern and combines the first and second code to form a 2D code that is applied to the scan chain array. A security signature register of the IC chip outputs a signature corresponding to a response from the scan chain array that is employable to detect changes to an IC design.


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