The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Oct. 17, 2022
Applicant:

Panjit International Inc., Kaohsiung, TW;

Inventors:

Chung-Hsiung Ho, Kaohsiung, TW;

Chih-Hung Chang, Kaohsiung, TW;

Chi-Hsueh Li, Tainan, TW;

Assignee:

PANJIT INTERNATIONAL INC., Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H10D 64/254 (2025.01); H01L 23/3171 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 24/16 (2013.01); H10D 64/258 (2025.01); H01L 2224/16227 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/30101 (2013.01); H01L 2924/3011 (2013.01);
Abstract

A metal oxide semiconductor (MOS) with multiple drain vias includes a semiconductor substrate, which is divided into a gate region, a source region and a drain region. On the same surface of the semiconductor substrate in the gate region, a connection layer is formed in the source region and the drain region with a low-resistance metal material. A plurality of conductive elements, such as solder balls, can be directly arranged on the connection layer, so that the MOS can be soldered to the circuit board through the conductive elements distributed on the same surface. In the drain region, there are a plurality of vias. The inside of each via is filled with the connection layer and extends to the inside of the semiconductor substrate. With the aforementioned structure, the MOS has the advantage of low on-resistance R.


Find Patent Forward Citations

Ho, Chung-Hsiung. (2025). Metal oxide semiconductor with multiple drain vias (U.S. Patent No. 12408407). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12408407

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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