The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Jun. 16, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Semyeong Jang, Hefei, CN;

Joonsuk Moon, Hefei, CN;

Deyuan Xiao, Hefei, CN;

Jo-Lan Chin, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10B 12/30 (2023.02); H10B 12/482 (2023.02); H10D 30/031 (2025.01); H10D 30/6757 (2025.01);
Abstract

A semiconductor structure includes: a base, including bit lines extending in a first direction and semiconductor channels on the bit lines that are respectively arranged at intervals, in which a semiconductor channel includes a first region, a second region and a third region arranged in sequence; a dielectric layer, located between two adjacent ones of the bit lines and on a surface of the semiconductor channel; a first gate layer, surrounding the dielectric layer of the second region and extending in a second direction; a second gate layer, surrounding the dielectric layer of the third region, which is spaced apart from the first gate layer in the direction perpendicular to the top surface of the bit line; and an insulation layer, located between the adjacent semiconductor channels on the same bit line and isolating the first gate layers and the second gate layers on the adjacent dielectric layers.


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