The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Dec. 05, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Mark I. Gardner, Cedar Creek, TX (US);

H. Jim Fulford, Marianna, FL (US);

Partha Mukhopadhyay, Jacksonville, FL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/00 (2025.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10B 12/30 (2023.02); H01L 25/0657 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10D 30/6735 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01);
Abstract

A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.


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