The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Nov. 08, 2023
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Yu Lee, Taoyuan, TW;

Teng-Hao Yeh, Hsinchu County, TW;

Hang-Ting Lue, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 5/06 (2006.01); G11C 16/08 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 5/063 (2013.01); G11C 16/08 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02);
Abstract

A 3D memory including a plurality of tiles, a bit line transistor structure, a first upper conductive layer, and a second upper conductive layer. The bit line transistor structure is disposed between a first sub-tile and a second sub-tile in the plurality of tiles. The first upper conductive layer includes a plurality of local bit lines, a plurality of local source lines and a conductive pattern. The plurality of local bit lines include a first group and a second group of local bit lines separated from each other, wherein two adjacent local bit lines are disposed between adjacent two local source lines. The second upper conductive layer includes a global bit line. The global bit line is electrically connected to the local bit lines through the conductive pattern. The 3D memory could be a 3D AND flash memory with high capacity and high performance.


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