Memory structure, manufacturing method thereof, and operating method thereof

Abstract

A memory structure includes insulating layers, gate layers, a first doping layer, channel layers, a columnar channel, second doping layers, a first dielectric layer, second dielectric layers, a third dielectric layer, and fourth dielectric layers. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The channel layers are connected to the first doping layer, in which the channel layers and the insulating layers are alternately stacked. The second doping layers surround the columnar channel and are connected to the channel layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the second doping layers and the gate layers. The third dielectric layer is between the columnar channel and the second doping layers. The fourth dielectric layers are between the channel layers and the gate layers.