The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
May. 17, 2021
Applicant:
Cree, Inc., Durham, NC (US);
Inventors:
Thomas J. Smith, Jr., Raleigh, NC (US);
Saptharishi Sriram, Cary, NC (US);
Assignee:
Wolfspeed, Inc., Durham, NC (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H03K 17/687 (2006.01); H10D 30/01 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/475 (2025.01); H03K 17/687 (2013.01); H10D 30/015 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01);
Abstract
An apparatus for reducing lag includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a gate control circuit configured to control a gate voltage of the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and an area between the gate and the drain.