logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12402309 B1

PDFFull Text
Date of Patent:
Aug. 26, 2025

Filed:

Jul. 14, 2021

Three-dimensional memory devices and fabricating methods thereof

Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Liang Chen, Hubei, CN;

Lei Xue, Hubei, CN;

Wei Liu, Hubei, CN;

Shi Qi Huang, Hubei, CN;

Assignee:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Attorney:

Conley Rose, P.C.

Primary Examiner:

Sue A Purvis

Assistant Examiner:

Seyon Ali-Simah Punchbeddell

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 43/40 (2023.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/022 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/89 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 43/40 (2023.02); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80001 (2013.01);
Abstract

A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an etch stop structure in a first wafer, forming a first through contact in contact with the etch stop structure, bonding the first wafer to a second wafer to electrically connect the first through contact to a CMOS device of the second wafer, and forming a through substrate contact penetrating a first substrate of the first wafer and the etch stop structure, and in electrically contact with the CMOS device through the first through contact.

Find Patent Forward Citations

Quick Actions:

Chen, Liang. (2025). Three-dimensional memory devices and fabricating methods thereof (U.S. Patent No. 12402309). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12402309

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…