The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

May. 17, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Sin-Yao Huang, Tainan, TW;

Jeng-Shyan Lin, Tainan, TW;

Shih-Pei Chou, Tainan, TW;

Tzu-Hsuan Hsu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 27/146 (2006.01); H10F 39/00 (2025.01); H10F 39/12 (2025.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H10F 39/011 (2025.01); H10F 39/014 (2025.01); H10F 39/026 (2025.01); H10F 39/182 (2025.01); H10F 39/199 (2025.01); H10F 39/807 (2025.01); H10F 39/811 (2025.01); H01L 24/13 (2013.01); H01L 2224/02233 (2013.01); H01L 2224/0225 (2013.01); H01L 2224/02251 (2013.01); H01L 2224/02255 (2013.01); H01L 2224/0226 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/0361 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/131 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/053 (2013.01); H10F 39/8053 (2025.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip including a substrate having an upper surface vertically below a top surface. A dielectric structure contacts the top surface of the substrate. A conductive structure is disposed in the substrate. The conductive structure includes an upper conductive body and conductive protrusions directly underlying the upper conductive body. The upper conductive body overlies the upper surface of the substrate. A bottom surface of the dielectric structure is disposed between a top surface and a bottom surface of the upper conductive body. An isolation structure is disposed in the substrate on opposing sides of the upper conductive body.


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