Memory device and method for reducing active power consumption thereof using address control

Abstract

The present disclosure provides a memory device, including a memory array, a tracking circuit, a memory controller, and a word line driver. A plurality of word lines are in communication with a plurality of memory cells of the memory array. The memory controller decodes a memory address of a memory access command to generate a decoded row address signal. The word line driver is configured to assert one of the plurality of word lines in response to the decoded row address signal. In response to detecting a switching event of a clock control signal derived from an input clock signal of the memory device, the memory controller asserts an tracking acceleration signal obtained from a tracking word line of the memory device to activate one or more first tracking arrays of the plurality of tracking arrays to pull down a voltage level of a tracking bit line.