The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Sep. 13, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Chen Zhang, Santa Clara, CA (US);

Kangguo Cheng, Schenectady, NY (US);

Juntao Li, Cohoes, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/3065 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/3065 (2013.01); H10D 30/0245 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/0193 (2025.01); H10D 84/85 (2025.01); H10D 84/853 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01);
Abstract

Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.


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