The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 11, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Cheng-Ta Wu, Hsinchu, TW;

Chiu Hua Chen, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2025.01); H01L 21/322 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/83 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 86/00 (2025.01); H10D 84/90 (2025.01);
U.S. Cl.
CPC ...
H10D 62/116 (2025.01); H01L 21/28035 (2013.01); H01L 21/3226 (2013.01); H01L 21/76202 (2013.01); H10D 30/0413 (2025.01); H10D 30/6739 (2025.01); H10D 30/6758 (2025.01); H10D 30/69 (2025.01); H10D 62/83 (2025.01); H10D 64/66 (2025.01); H10D 64/661 (2025.01); H10D 64/671 (2025.01); H10D 84/0112 (2025.01); H10D 84/0165 (2025.01); H10D 84/038 (2025.01); H10D 86/201 (2025.01); H01J 2237/0437 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1517 (2013.01); H10D 84/957 (2025.01);
Abstract

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.


Find Patent Forward Citations

Loading…