The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Aug. 12, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Lorenzo Fratin, Buccinasco, IT;

Enrico Varesi, Milan, IT;

Paolo Fantini, Vimercate, IT;

Thomas M. Graettinger, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 63/845 (2023.02); H10N 70/066 (2023.02);
Abstract

Methods, systems, and devices for pillar and word line plate architecture for a memory array are described to support a memory array that may include a word line plate at each vertical level of the memory array, where the word line plate may be coupled with each memory cell of a word line tile at the respective level. The memory array includes multiple pillars, where each pillar includes two or more electrodes that run the vertical length of the pillar and which are separated by an insulating dielectric material. Each electrode of the pillar is coupled with a corresponding set of memory cells, with each memory cell located at a different level of the array. An electrode of the pillar mis addressed, along with a word line plate of the memory array, to access a memory cell associated with the electrode and word line plate.


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