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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12396171 B1

PDFFull Text
Date of Patent:
Aug. 19, 2025

Filed:

Mar. 31, 2022

Method of fabricating three-dimensional nand memory

Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Yaqin Liu, Hubei, CN;

Kun Zhang, Hubei, CN;

Linchun Wu, Hubei, CN;

Wenxi Zhou, Hubei, CN;

Assignee:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Attorney:

HANLEY, FLIGHT & ZIMMERMAN, LLC

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/78 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/7806 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02);
Abstract

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming a dielectric stack on a substrate, and forming a first opening penetrating through the dielectric stack and extending into the substrate from a first side of the dielectric stack. The method also includes forming a first layer and a second layer inside the first opening from the first side of the dielectric stack, wherein the first layer covers a sidewall and a bottom of the first opening. The method further includes removing a portion of the first layer located at the bottom of the first opening from a second side of the dielectric stack to expose a portion of the second layer. The method further includes forming a second semiconductor layer from the second side of the dielectric stack to contact the exposed portion of the second layer.

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