The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Aug. 22, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Semyeong Jang, Hefei, CN;

Deyuan Xiao, Hefei, CN;

Joonsuk Moon, Hefei, CN;

Jo-Lan Chin, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H10B 12/482 (2023.02); H01L 23/5222 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53271 (2013.01); H01L 23/53295 (2013.01);
Abstract

Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the present disclosure includes: providing a substrate, the substrate being provided with first trenches arranged in a same direction; forming protective layers on side walls of the first trenches; forming second trenches at bottoms of the first trenches, the second trenches being wider than the first trenches; forming first spacers on side walls of the second trenches to reduce opening sizes of the second trenches; filling the first trenches and the second trenches to form second spacers, and forming voids in the second trenches; forming third trenches in the substrate, the third trenches being perpendicular to the first trenches; and forming bit lines in the third trenches.


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