The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Jun. 14, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chieh Lee, Hsinchu, TW;

Chia-En Huang, Hsinchu, TW;

Yi-Ching Liu, Hsinchu, TW;

Wen-Chang Cheng, Hsinchu, TW;

Yih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4091 (2006.01); G11C 5/06 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 5/063 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); H03K 19/20 (2013.01);
Abstract

A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.


Find Patent Forward Citations

Loading…