The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Aug. 04, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Meng-Sheng Chang, Hsinchu County, TW;

Chia-En Huang, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/18 (2006.01); G11C 8/14 (2006.01); H01L 23/522 (2006.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01); H10B 20/25 (2023.01);
U.S. Cl.
CPC ...
G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H01L 23/5252 (2013.01); H01L 23/5283 (2013.01); H10B 20/25 (2023.02);
Abstract

A method of forming a memory cell includes: providing a semiconductor substrate; forming an active region on the semiconductor substrate; providing a first conductive line over a first portion of the active region to form a first transistor coupled to a bit line of the memory cell; providing a second conductive line over a second portion of the active region to form a second transistor coupled to the bit line of the memory cell; and providing a third conductive line over a third portion of the active region to form a third transistor coupled to a first word line of the memory cell. The first transistor and the second transistor are disposed on two sides of the third transistor, and the third transistor electrically couples the first transistor to the second transistor. A threshold voltage of the second transistor is different from a threshold voltage of the first transistor.


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