The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Aug. 23, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Semyeong Jang, Hefei, CN;

Joonsuk Moon, Hefei, CN;

Deyuan Xiao, Hefei, CN;

Jo-Lan Chin, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2025.01); H01L 21/321 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/28097 (2013.01); H01L 21/28123 (2013.01); H01L 21/28247 (2013.01); H01L 21/32105 (2013.01); H10D 30/014 (2025.01); H10D 30/6728 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 62/122 (2025.01);
Abstract

Embodiments relate to a semiconductor structure and a fabrication method. The method includes: providing a substrate, where a first trench is formed in the substrate; forming a first dielectric layer and a protective material layer in the first trench, where the first dielectric layer is positioned between the protective material layer and the substrate, and an upper surface of the first dielectric layer is lower than an upper surface of the substrate, to expose a portion of a side wall of the first trench; forming a second dielectric layer on the exposed side wall of the first trench; and filling the second trench to form a work function structure, where the work function structure includes a first work function layer and a second work function layer, where the second work function layer is positioned on an upper surface of the first work function layer.


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