The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Jun. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shahaji B. More, Hsinchu, TW;

Shu Kuan, Keelung, TW;

Cheng-Han Lee, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 23/544 (2006.01); H10D 62/832 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/751 (2025.01); H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/30625 (2013.01); H01L 21/308 (2013.01); H01L 23/544 (2013.01); H10D 62/832 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/0191 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 84/859 (2025.01); H01L 2223/54426 (2013.01);
Abstract

A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.


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