The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Nov. 24, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Hung Yeh, Hsinchu, TW;

Wun-Jie Lin, Hsinchu, TW;

Jam-Wem Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 3/08 (2006.01); H02H 1/00 (2006.01);
U.S. Cl.
CPC ...
H02H 3/08 (2013.01); H02H 1/0007 (2013.01);
Abstract

An electrostatic discharge (ESD) protection circuit includes a first and second diode in a semiconductor wafer, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer. The first diode is coupled between an input output (IO) pad and a first node. The second diode is coupled to the first diode, and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled to the first and second node, and between the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a reference voltage supply. The second diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit. The first conductive structure is configured to provide a reference voltage to the first signal tap region.


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