The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Jul. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yi-Ching Liu, Hsinchu, TW;

Yih Wang, Hsinchu, TW;

Chia-En Huang, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); H01L 23/3157 (2013.01); H01L 24/24 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24146 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.


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