The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Aug. 23, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;

Inventors:

Li-Hsien Huang, Zhubei, TW;

Hsueh-Lung Cheng, Hsinchu, TW;

Yao-Chun Chuang, Hsinchu, TW;

Yinlung Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/73 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/96 (2013.01); H01L 25/18 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05555 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05664 (2013.01); H01L 2224/06134 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13164 (2013.01); H01L 2224/16258 (2013.01); H01L 2224/19 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/95001 (2013.01); H01L 2224/96 (2013.01);
Abstract

A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.


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