The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Oct. 11, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gilbert W. Dewey, Beaverton, OR (US);

Rafael Rios, Austin, TX (US);

Van H. Le, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/66 (2025.01); H01L 21/02 (2006.01); H01L 21/465 (2006.01); H10D 30/62 (2025.01); H10D 62/82 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10D 64/671 (2025.01); H01L 21/02565 (2013.01); H01L 21/0262 (2013.01); H01L 21/465 (2013.01); H10D 30/6219 (2025.01); H10D 62/82 (2025.01); H10D 64/021 (2025.01); H10D 64/259 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 99/00 (2025.01);
Abstract

FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.


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