The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Jul. 27, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Sai-Hooi Yeong, Zhubei, TW;

Chi-On Chui, Hsinchu, TW;

Chien-Ning Yao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/40 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/701 (2025.01); H10D 30/024 (2025.01); H10D 30/0415 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 62/118 (2025.01); H10D 64/033 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a transistor which includes a source/drain feature adjoining an active region, and a gate stack over the active region. The semiconductor device structure further includes a capacitor above the transistor, the capacitor including a bottom electrode layer on the gate stack and a ferroelectric layer on the bottom electrode layer. The ferroelectric layer is made of a Hf-based dielectric material. The semiconductor device structure further includes gate spacer layers surrounding the gate stack, the bottom electrode layer and the ferroelectric layer.


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