The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Jul. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Han-Jong Chia, Hsinchu, TW;

Yi-Ching Liu, Hsinchu, TW;

Chia-En Huang, Hsinchu County, TW;

Sheng-Chen Wang, Hsinchu, TW;

Feng-Cheng Yang, Hsinchu County, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H01L 23/522 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H10B 51/10 (2023.02); H10B 51/30 (2023.02);
Abstract

A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.


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