The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Feb. 26, 2024
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Jun Liu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 21/02 (2006.01); H01L 21/20 (2006.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 21/02013 (2013.01); H01L 21/2007 (2013.01); H01L 25/0657 (2013.01); H10B 12/09 (2023.02); H10D 84/038 (2025.01); H10D 88/01 (2025.01);
Abstract

In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.


Find Patent Forward Citations

Liu, Jun. (2025). Bonded semiconductor devices having processor and static random-access memory and methods for forming the same (U.S. Patent No. 12376278). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12376278

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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